The present invention relates to a semiconductor device and to a method for fabricating it. The present invention relates in particular to a VLD edge termination with a near-surface zone having or formed from an opposite conductivity type.
When forming semiconductor devices, for example semiconductor circuit elements in an underlying semiconductor material region, certain edge structures are required in order to achieve certain physical or circuitry properties of the corresponding semiconductor element or of the component. The edge structures in each case relate to the edge region which develops in the edge of a semiconductor element or of a semiconductor device. With regard to the wafer, this may quite easily be an area in the interior of the wafer at a location remote from the edge of the wafer. The edge position and therefore the corresponding edge structure then apply after integrated circuits and/or discrete components produced have been singulated.
Previous procedures used to produce edge structures have been relatively complex, and a large number of different mask processes, which are matched and adjusted to one another, are frequently required in order to enable the required edge structures with their specific properties to be produced.
High-voltage semiconductor components require edge structures in order to achieve the necessary dielectric strength. These edge structures have hitherto been very complex. Examples include SIPMOS and IGBT power transistors and high-voltage diodes.
The main role of a high-voltage chip edge is to control the electrical field strength in the region between the active area and the sawn edge of the component. To avoid premature breakthroughs in the blocking state, the electrical field strength at the edge must not exceed the maximum values which occur in the active region. The objective is for the equipotential lines to be passed in a defined way out of the interior of the component in the chip edge to the surface, that is, the invention relates inter alia to field line or equipotential line management.
In this context, it should be ensured that curves and the density of the equipotential lines do not cause any excessively high field, that is, cause premature punch-throughs in the component, for example as a result of an avalanche breakdown in Si or as a result of a dielectric breakdown in oxide and passivation layers.
A virtually ideal distribution of the surface field strength ensures a so-called VLD edge termination (VLD=Variation of Lateral Doping), in which the gradual attenuation of the lateral doping profile is set in such a way that a constant electrical field strength results at the surface of the semiconductor over virtually the entire edge width.
The VLD principle has been described in R. Stengl et al., IEEE Trans. ED 33, 426 (1986). A method for realizing a VLD high-voltage edge with a low junction depth can be realized, for example, using special mask techniques for lateral dose attenuation when introducing the dopant via ion implantation. A method of this type also comprises, for example, introducing a dopant in the case of ion implantation through a resist mask with a laterally varying opening ratio and subsequently causing the doping to flow by means of a high-temperature process.
FIG. 1 diagrammatically depicts the structure of an edge termination of this type. To keep the chip outer edge, at which the sawn edge is present, potential-free, a channel stopper is generally incorporated, at which further propagation of the space charge region is to be stopped.
FIG. 2 illustrates the result of a simulation of the potential distribution for a high-voltage diode, as designed for a rated voltage of 3.3 kV, having an edge termination of this type. The simulations were carried out using the BREAKDOWN program J. Pelka, Dissertation, TU Berlin (1983).
This example is specifically based on the following structural data:
The n-doped base material has a resistivity of 350 Ωcm and a thickness of 375 μm. The vertical and lateral diffusion depth of the p+ anode area is 6 μm, and the surface concentration of the latter is 5·1018 cm−3.
A surface concentration of 1·1018 cm−3 was used for the n+ channel stopper. Its width is 10 μm, and the total edge width is 860 μm. The VLD zone extends as far as the channel stopper, and the maximum junction depth at the anode is equal to the latter. The depth of the cathode-side n+ zone and its edge concentration were set at 20 μm and 2·1015 cm−3.
The maximum blocking capability in the bulk of the component with these basic dimensions is approximately 4800 V.
When optimizing the lateral dose profile and the value for the VLD maximum dose with a view to keeping the electrical field strength at the semiconductor surface at a constant value, an implantation dose of 1.4·1012 cm−2 results in the profile of the lateral acceptor dose distribution, the potential distribution and the field distribution illustrated in FIG. 3. The reverse voltage is in this case 4525 volts.
On account of the relatively low edge width, the reduction in potential before the channel stopper is built up slightly and a field strength peak is formed at this location. Nevertheless, if the edge is too narrow, the channel stopper is unable to prevent the space charge region from penetrating into the region of the vertical chip edge, FIG. 2. Since the sawn edge is normally present here, this at least leads to increased leakage currents and in extreme cases can even lead to an electrical sparkover from the chip edge to the anode.
Moreover, the field strength peak at the channel stopper constitutes a further problem, because it is associated with a high field gradient which represents the driving force for the build-up of charge carrier peaks which may be caused by the separation of external charges in or on the passivation layer. In the case of a dielectric passivation, this effect ultimately leads to a very strong and undesirable drift in the blocking capability and to surface breakdowns at the n+ channel stopper R. Stengl and E. Falck, IEEE Trans. On Electron Dev., Vol. 38, No. 9, September 1991, pp. 2181-2188.
To prevent the space charge region from penetrating into the edge region, the edge would have to be made wider, in this case at least 1200 μm. Although this would reduce the field peak at the channel stopper, it would not eliminate it altogether.